1. The Field of the Invention
The present invention relates to systems and methods for amplifying electrical signals. More specifically, the present invention relates to systems and methods for enhancing charge transfer amplifier gain.
2. The Prior State of the Art
There are many circuits and methods conventionally available for amplifying an electrical signal. One type of amplifier is called a charge transfer amplifier. Charge transfer amplifiers operate on the principle of capacitive charge sharing. Voltage amplification is achieved by transferring a specific amount of charge between appropriately sized capacitors through an active device.
FIG. 1 illustrates a charge transfer amplifier 100 that utilizes an nMOS transistor N1 to transfer charge between capacitors CT and CO. The operation of the nMOS charge transfer amplifier 100 will now be described in order to illustrate the basic principle of charge transfer amplification.
The nMOS charge transfer amplifier 100 operates in a cycle of three phases including a reset phase, a precharge phase, and an amplify phase. FIG. 2 is a signal timing diagram for two input signals S1 and S2 with respect to the cycle phase that the nMOS charge transfer amplifier 100 is operating in whether that phase be (a) the reset phase, (b) the precharge phase or (c) the amplify phase. The two input signals S1 and S2 control corresponding switches S1 and S2 of FIG. 1. Switch !S1 corresponds to the inverse phase of the input signal S1.
The cycle begins with the (a) reset phase in which both input signals signal S1 and S2 are high indicating that switches S1 and S2 are closed and that switch !S1 is open. Since the switch S1 is closed, the upper terminal of capacitor CT (i.e., node A) is discharged through the switch S1 to voltage Vss. Since the switch S2 is closed, the upper terminal of capacitor CO (i.e., node B is charged to a voltage VPR. The open switch !S1 prevents static current from flowing through the nMOS transistor N1.
After the reset phase is the (b) precharge phase in which the signal S1 is low indicating that switch S1 is open and the switch !S1 is closed, and in which the signal S2 is high indicating that the switch S2 remains closed. Thus, the upper terminal of the capacitor CO (i.e., node B) remains charged at the precharge voltage VPR. This precharge voltage VPR is high enough that current flows from node B to the capacitor CT (and node A) through the nMOS transistor N1 and the switch !S1. For example, if the precharge voltage VPR is at least equal to the input voltage VIN at the gate of the nMOS transistor N1, then the discharge continues until the voltage at the capacitor CT increases to be equal to the input voltage VIN minus the threshold voltage (hereinafter xe2x80x9cVTNxe2x80x9d) of the nMOS transistor N1. At that point, the nMOS transistor N1 enters the cutoff region and current flow to the capacitor CT substantially ceases. Thus, at the end of the precharge phase, the capacitor CO ideally has a voltage of VPR while the capacitor CT has a voltage of VIN -VTN.
After the precharge phase is the (c) amplify phase in which both signals S1 and S2 are low indicating that both switches S1 and S2 are open. During the amplify phase, an incrementally positive input voltage change xcex94VIN at the gate of the nMOS transistor N1 will cause the nMOS transistor N1 to turn on thereby allowing current to flow through the nMOS transistor N1 until the nMOS transistor is again cutoff. For small incrementally positive voltage changes xcex94VIN, the nMOS transistor N1 will cutoff when the voltage on the upper terminal of the capacitor CT (i.e., node A) increases by the incrementally positive voltage change xcex94VIN. The amount of charge transferred to the capacitor CT in order to produce this effect is equal to the incrementally positive voltage change xcex94VIN times the capacitance CT of the capacitor CT.
Since the charge xcex94VINxc3x97CT transferred to the capacitor CT came from node B through transistor N1, the charge xcex94VINxc3x97CT was drawn from the capacitor CO. Thus, the voltage at the capacitor CO and the output voltage VOUT will change by xcex94VINxc3x97(CT/C0). If the capacitance CT is greater than the capacitance C0, amplification occurs.
One advantage of the nMOS charge transfer amplifier 100 is that the voltage gain and power consumption maybe controlled by setting the capacitance of the capacitors CO and CT as well as by setting the capacitance ratio CT/C0. Another advantage of charge transfer amplifiers in general is that the circuit performance is generally unaffected by the absolute values of the supply voltage Vss and Vdd as long as these voltages permit proper biasing during the reset and precharge phases. In other words, charge transfer amplifiers have high supply voltage scalability in that no changes are needed for a charge transfer amplifier to operate using a wide range of supply voltages Vss and Vdd.
Although the nMOS charge transfer amplifier 100 has these advantages, amplification only occurs in the nMOS charge transfer amplifier 100 if the input gate voltage change xcex94VIN is positive. A negative gate voltage change xcex94VIN would only cause the nMOS transistor N1 to enter deeper into the cutoff region. Thus, charge transfer between node A and node B would be stifled thereby preventing amplification.
FIG. 3 shows a conventional CMOS charge transfer amplifier 300 that amplifies using positive input voltage changes xcex94VIN as well as negative input voltage changes xcex94VIN. The CMOS charge transfer amplifier 300 includes the nMOS charge transfer amplifier 100 described above. For clarity, the nMOS charge transfer amplifier 100 is shown in FIG. 3 as being enclosed by a dotted box.
The CMOS charge transfer amplifier 300 also includes a partially overlapping pMOS charge transfer amplifier 301 which is shown in FIG. 3 enclosed by a dashed box for clarity. The pMOS charge transfer amplifier 301 shares the voltage input line 302, the voltage output line 303 and the precharge line 304 with the nMOS charge transfer amplifier 100. The pMOS charge transfer amplifier 301 is structured similar to the nMOS charge transfer amplifier 100 except that the pMOS charge transfer amplifier 301 uses a pMOS transistor P1 instead of an nMOS transistor N1 for transferring charge between capacitors. Also, node Axe2x80x2 of the pMOS charge transfer amplifier 301 is reset to a high voltage Vdd instead of the low voltage Vss and is capacitively coupled to the high voltage Vdd instead of the low voltage Vss.
The general operation of the pMOS charge transfer amplifier 301 for negative input voltage changes xcex94VIN is similar to the operation of the nMOS charge transfer amplifier 100 for positive voltage changes xcex94VIN Thus, the input signals S1 and S2 of FIG. 2 are used in the operation of the CMOS charge transfer amplifier 300. Due to the complementary nature of the nMOS charge transfer amplifier 100 and the pMOS charge transfer amplifier 301, the CMOS charge transfer amplifier 300 amplifies for both positive and negative input voltage changes xcex94VIN.
The CMOS charge transfer amplifier 300 is advantageous in that it consumes no static current, capitalizes on parasitic capacitors, is memory less, operates over a wide voltage supply range, produces little noise, is insensitive to threshold voltage fluctuations, and comprises relatively few devices. However, it would represent an advancement in the art to create a system and method in which the gain of the charge transfer amplifier is enhanced without giving up any of the advantages inherent in the charge transfer amplifier.
The foregoing problems in the prior state of the art have been successfully overcome by the present invention, which is directed to an enhanced gain amplifier for use with charge transfer amplifiers. A positive capacitive feedback mechanism is attached from the output terminal to an intermediate terminal of the charge transfer amplifier. This reduces the capacitance viewed at the intermediate terminal of the charge transfer amplifier thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of the charge transfer amplifier.
In one embodiment, the first stage charge transfer amplifier is a differential mode charge transfer amplifier. The second stage amplifier may also be a differential mode charge transfer amplifier with no input coupling portion required. The positive capacitive feedback occurs by capacitively coupling one output terminal of the second stage differential mode charge transfer amplifier to an output terminal of the first stage differential mode charge transfer amplifier. Similarly, the other output terminal of the second stage differential mode charge transfer amplifier is capacitively coupled to the other output terminal of the first stage differential mode charge transfer amplifier. This positive capacitive feedback mechanism increases the gain of the first differential mode charge transfer amplifier. This additional gain is fed to the second stage differential mode charge transfer amplifier thereby improving the gain of the entire cascaded differential mode charge transfer amplifiers. In one embodiment, the feedback capacitors are structured similar to transistors within the second stage differential mode charge transfer amplifiers to improve the performance of the cascaded differential mode charge transfer amplifiers over a wide range of temperatures, bias conditions and threshold voltages.
Additional advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or maybe learned by the practice of the invention as set forth hereinafter.